-------------------------------------------------------------------------------
--
-- Title       : clk_gen
-- Design      : BDE_demo
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : c:\Users\vincenti\Desktop\testworkspace\wkspace\BDE_demo\src\clk_gen.vhd
-- Generated   : Fri Feb 13 16:30:12 2015
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {clk_gen} architecture {clk_gen}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity clk_gen is
	port(
		clk : out STD_LOGIC := '0' 
		);
end clk_gen;

architecture clk_gen_arch of clk_gen is
begin
	clk_gen: process(clk)
	begin
		clk <= not clk after 50ns; 
	end process;
	
end clk_gen_arch;
